Development of a low-power LMS adaptive filter for EEG signals-Edición Única

Abstract

The aim of this thesis is the evaluation of power consumption rates for different LMS adaptive digital filter architectures. The filter is used to attenuate the power line interference in the recording of EEG signals. A Simulink-based design flow is utilized to provide rapid hardware evaluation of the architectures proposed, from algorithm design to physical layout. To demonstrate the advantages of this design flow, a pipelined filter was implemented in 0.35 µm technology from AMS. In order to simplify the power consumption, delay, and area estimation, and given the large number of transistors contained in the adaptive filters, a characterization methodology is introduced. Due to the high regularity of the filter, the basic functional units were characterized using this methodology. Finally, this thesis work analyzes the performance and power consumption of five dedicated DSP architectures implementing the LMS algorithm. Low-power operation was accomplished by using voltage scaling while the throughput is maintained by means of pipelining and relaxed look-ahead techniques. Simulation results show that if the filters were to be run at their maximum allowable clock frequency, power savings at around 75% and up can be obtained by using a supply voltage lower than 1.95 V. For practical purposes, the area overhead can be neglected.