A VHDL-AMS Transistor Level Model of a UHF RFID Tag for System Simulation -Edición Única

The fabrication processes of Radio Frequency Identification Systems implies a large and an expensive development effort as well as very long testing periods. System modeling and cosimulation is an important approach for reduce the time to place a product into the market. This thesis presents a transistor level model of a UHF RFID tag, implemented with VHDL-AMS, for both (l)early detection of mixed signal design problems and (2)transistor level estimation of the power consumption in analog and digital subsystems. The transistor model used in the RFID tag model was implemented in VHDL-AMS and it was modeled according the characteristics of a long channel transistor. The power consumption was estimated using analog and digital components. Analog power consumption was calculated from the electric parameters of the transistor model, and digital power consumption from the switching at the output of the gates in the tag model. The functional simulation of the tag was 100% compatible with the implemented communication protocol, and the power consumption had a maximum improvement of 27.15% compared with similar research and development efforts.