Profiling and Analysis of Irregular Memory Accesses of Memory-Intensive Embedded Programs-Edición Única

As memory transactions have become a significant contributor to increment the amount of power consumption and the reduction of system performance, this work presents a methodology to select fragments of program code to map the most used memory locations to a small, fast and energy efficient memory (SPM scratch pad memory). This methodology achieves a performance improvement, a reduction of energy consumption and overcomes the memory wall problem. The work is a part of the project “Design Space Exploration of Memory-Intensive Embedded Systems”, which has led us to the need of building a framework to perform a study of how the memory behavior impacts in the memory hierarchy efficiency in terms of power consumption. The methodology proposes the method to map to a SPM to validate this framework. The method is divided into two stages: the trace generation and the pos-simulation study. From each study, important information about the program behavior is gathered to calculate, to identify and to allocate the hot spots of memory accessing. In both stages this information was used to propose a better memory allocation that increases performance and reduces the traffic of the chip. To validate the results, the same methodology was implemented for several scientific codes in different configurations. The results show that SPM configuration reduces the power consumption up to by 65% with an average reducuction of 55% compared to the 45% obtained from the cache configuration